The present invention relates to analog device testing, and more particularly, to a method and system for performing circuit continuity testing of analog devices having sensitive input nodes.
Generally, an analog device, such as a operational amplifier, has multiple input terminals, also known as input nodes, that are adapted to receive voltage or current signals. Typically, when a continuity test of the device is performed, additional capacitive or impedance loading is realized at the nodes. The nodes themselves are sensitive and any additional loading during testing will often cause the device to lose its functionality.
One conventional method of testing for circuit continuity of an analog device having sensitive input and output nodes has been to isolate the nodes from the test equipment 12 using external relays 14, 16, as illustrated in FIG. 1. These relays isolate the respective device nodes from any external capacitance or impedance created when the nodes are directly coupled to test instrument 12. However, this technique becomes inadequate when multi-site testing of the analog device is conducted, wherein typically 2 to 32 analog devices are tested in parallel, and thus, the number of relays needed to properly isolate the nodes becomes unreasonable.
Accordingly, there exists a need for a method and system that effectively isolates the input and output nodes of the analog device when a continuity test is performed, thereby eliminating the negative effects of any additional impedance and capacitance loading thereon during testing. Furthermore, such a method or system would allow for parallel testing at the nodes without the use of external isolation relays.
The present invention provides technical advantages as a method and system of isolating the input and output nodes of an analog device with resistors during a continuity test without using numerous relays. In isolating the nodes and removing the unwanted capacitance and impedance loading thereon, the invention allows simultaneous testing of multiple nodes to be performed in parallel. This reduces testing time and permits direct testing on the nodes of multiple devices without the use of external circuit relays.
In one preferred embodiment, the invention is a method of performing an internal circuit continuity test on an analog device that has a pair of input terminals comprising input nodes. Each of these input nodes are coupled to respective input terminals and separate respective output terminals of a receiving testing circuit comprising a plurality of resistors configured in parallel. The method is achieved, first, by providing a first voltage input via a resistor to the first input of the receiving circuit which responsively produces a voltage drop sensed at the first output terminal. The node voltage is then measured by the testing device connected to the first input. A diode voltage drop sensed at the first input is indicative of the internal circuit continuity of the analog device. Conversely, sensing the applied voltage is indicative of no continuity. This method is repeated for each input and output node, simultaneously, to allow expedited testing of all nodes in parallel, without relays.
In another embodiment, the invention is a system that has an analog device such as a differential amplifier, which has a first and second input terminal, forming a first and second input node, respectively, and a pair of output terminals. The system has a test interface first input comprising a first resistor which is connected to the first node and is adapted to provide an input voltage. A test interface first output includes a second resistor, also connected to the first node, that receives a voltage output responsive to the applied input voltage that is indicative of the internal circuit continuity of the analog device. A voltage drop is sensed at the test interface first output due to a diode clamp circuit located therein. The voltage output is measured via the second resistor with a testing device, such as voltage or current meter. This testing structure, providing a separate resistor isolated input and output for each node under test, allows multiple nodes to be tested simultaneously, in parallel, without relays.